I > dont know if the problem is with my code or with alteras simulator > or compiler for quartus II, and because I havent money to purchase > leonardo spectrum and modelsim i have to think about another way to do > it to continue designing a ppp packet processor. I thought > of using a fifo whith pointers, but in my blocks the byte arrives as a > std. If you use Altera can you get for free a Leonardo front end? I had a look at your code. In fact it looks very regular. One process subsequently write the next byte on the next position in the 8. The read process is a little biut more complicated, but still regular. In a state i it checks wether: the pattern is a flag => then it generates a stuff byte and in the clock period an exor operation with the data is performed with flag otherwise the data in cola is going to the output. I tried to make use of the regular structure. Here my first attemp (no guarentee, no simulation performed etc.) After this you find a synthesisable solution. But first the straighforward one: LIBRARY ieee; USE ieee. END fifo. 0; - - Architecture Body ARCHITECTURE fifo. The index i is the state. In the read process an additional variable flag. This is probably not synthesisable. Synthesis tools don't like: cola (8*(i+1)- 1 downto 8*i) < = datos; if i is NOT a constant. However a trick to solve this problem is using a for loop. The index variable in a for loop is a constant! So the trick is: put a for loop around the code and check if the loop variable is equal with i (this will exactly occurs ones). Replace in the bode of the for loop the non constant i with the constant loop variable and since there was a check 'loop variable'=i the behaviour is unchanged. The synthesis tool I use needed 9. Remember that cola needs already 8. It allows to save MCU time wasted for handling HDLC/SDLC features like bit stuffing. As said before no guarantee (even not simulated!) but maybe it gives you a way how to solve it. Egbert Molenkamp ARCHITECTURE fifo. About vhdl code bit stuffing. Program to implement the data link layer framing method bit stuffing Page Link: Program to. FPGA BASED CAN PROTOCOL CONTROLLER. Testing the program code in. The data blocks arrive in a serial bit stream and they are coded by the method of 'bit stuffing'. University Program; Online Demonstrations. Bit stuffing and unstuffing. Verilog; VHDL; Testbench language: Verilog. SDLC Controller January 15. VHDL Source RTL available at extra cost.
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